This invention relates to a semiconductor driver circuit which is based on metal insulator-oxide field effect transistors (hereinbelow, abbreviated to "MOS-FET's") and further includes a bipolar transistor in combination therewith, which driver circuit has an operating speed higher than in prior art driver circuits.
Heretofore, in a C-MOS (Complementary-MOS) circuit wherein an enhancement type P-channel MOS-FET and an enhancement type N-channel MOS-FET are simultaneously integrated in an identical chip, a driver circuit as shown in FIG. 1 has been employed. Referring to the figure, numeral 1 designates an input terminal, numeral 2 an output terminal which is accompanied with a load capacitance 3, and numeral 4 a power supply terminal. P.sub.1 indicates a P-channel MOS-FET, while N.sub.1 indicates an N-channel MOS-FET. V.sub.DD denotes a positive supply voltage. The C-MOS driver circuit composed of the MOS-FET's (P.sub.1, N.sub.1) has the disadvantage that the load capacitance 3 is large and that in a case of driving it at high speed, the dimension (for example, channel width W) of the MOS-FET P.sub.1 must be made large. Accordingly, the area occupied by the driver circuit becomes large, which is a serious loss with regard to the density of integration.
The inventors have therefore provided an improved driver circuit shown in FIG. 2 in Japanese Patent Application No. 52-1490. Referring to the figure, P.sub.2 designates a P-channel MOS-FET whose drain and source are highly doped p-type layers formed in an n-type semiconductor substrate. Each of N.sub.2 and N.sub.3 indicates an N-channel MOS-FET whose drain and source are highly doped n-type layers formed within a well of a p-type layer provided in the surface of the substrate. Shown at B.sub.1 is a planar type bipolar transistor whose base is a p-type layer provided in the surface region of the substrate, whose collector is the substrate and whose emitter is a highly doped n-type layer provided within the base of the p-type layer. Characteristic of the prior art in FIG. 2 is that the bipolar transistor is integrated on the same chip and that a driver circuit is constructed of interconnections illustrated in the figure. When the input terminal 1 is at the ground potential, the MOS-FET's N.sub.2 and N.sub.3 are nonconductive, whereas the MOS-FET P.sub.2 is conductive. Current flows from the power supply terminal 4 to the base of the bipolar transistor B.sub.1, and the bipolar transistor B.sub.1 becomes conductive, so that the output terminal 2 is charged to a high potential.
When the input terminal 1 is at a high potential, the MOS-FET P.sub.2 is rendered nonconductive and also the bipolar transistor B.sub.1 is rendered nonconductive, and the MOS-FET N.sub.2 is rendered conductive, so that the output terminal becomes the ground potential. In the transition of the input terminal 1 from the high potential to the ground potential, high current flows from the power supply terminal 4 and through the bipolar transistor B.sub.1, and the load capacitance 3 can be charged at high speed.
For the transistor P.sub.2, only a driving capability enough to charge the junction capacitance which is formed by the base and collector of the transistor B.sub.1, is needed. As a result, the size of the transistor P.sub.2 becomes small, and the area occupied by the driver circuit is reduced. Besides, the base width of the bipolar transistor B.sub.1 can be made small in such a way that the diffusion depth of the highly doped n-type layer which is to become the emitter of the bipolar transistor B.sub.1 is made greater than the diffusion depth of the highly doped n-type layers which are to become the source and drain of the ordinary N-channel MOS-FET. In this case, the bipolar transistor B.sub.1 has a small base width and a high current gain h.sub.FE, which contributes further greatly to the enhancement of the operating speed of the driver circuit.
The N-channel MOS-FET N.sub.3 serves to abruptly lower the potential of the base of the bipolar transistor B.sub.1 to the ground potential through this transistor N.sub.3 at the time of the transition of the potential of the input terminal 1 from the ground potential to the high potential. This is advantageous for enhancing the operating speed and reducing the power dissipation.
FIG. 3 is a circuit connection diagram of a modification of the driver circuit in FIG. 2. A P-channel MOS-FET P.sub.3 can raise the potential of the output terminal 2 up to the supply voltage V.sub.DD when the input terminal 1 lies at the ground potential. Thus, it enhances the operating performance of a succeeding circuit connected to the output terminal 2.
The prior art devices illustrated in FIGS. 2 and 3 can provide driver circuits which occupy only a small area and have high speed performance. It is a disadvantage of these driver circuits, however, that when they are employed as an output buffer circuit etc., they cannot be used as the so-called tri-state or three-state type which assumes the three values of logic "0", "1" and "float".
More specifically, in a case where the capacity is made large by the use of a large number of IC memories which are constructed of limited works, the OR of information read out from the respective IC memories needs to be taken in points of the packaging space and the price. In order to make it possible to construct the so-called wired OR with which the OR function can be realized merely by connecting the output terminals by an electric wire, the data output circuits of the respective memory IC's must be constructed by the tri-state system. That is, it is required that only an IC memory chip selected by a chip select signal is connected with a data bus, whereas the others are disconnected from the data bus and are in the float or high impedance state.